The present invention relates generally to a bus arrangement which interconnects a number of modules or components in a digital system and more particularly to a synchronous bus arrangement and associated method for providing high speed, efficient digital data transfer between the modules. Implementation of the bus arrangement is contemplated at chip level, forming part of an overall integrated circuit, and is also contemplated as interconnecting discrete modules within an overall processing system.
Many bus structures have been implemented for purposes of interconnecting modules in a digital system. Module interfacing may generally be performed with relative ease when all of the modules are designed in accordance with the same set of design parameters (i.e., rules) such as, for example, those of a particular manufacturer. However, in the instance of modules designed by different manufacturers or obtained from different sources, complex interface problems may be introduced which, in turn, require significant special provisions (typically in the form of logic circuitry) in order to properly interface with a bus structure.
While the concept of modular components was initially implemented using discrete modules, it should be appreciated that there now exists an industry wide movement toward the use of modular components (i.e., functional blocks) at the integrated circuit level. This movement toward modular design in integrated circuit manufacturing has been fueled, at least in part, by the desire to manage the continually increasing complexity and overall size of integrated circuit chips. As a result of the modular design methodology, however, single IC chips may now incorporate modules which are designed to different standards and which are provided by different sources such that complex interface problems are now present at the chip design level. In an environment such as, for example, a custom IC manufacturing house using modules designed by various sources, such interface problems can be particularly troublesome.
In the prior art, module interface problems are typically resolved by using logic circuitry which resides in the bus structure between the modules. This approach was initially applied for interfacing discrete modules and, as one would expect, later applied for interfacing modules integrated within a single IC. As will be seen, the use of logic circuitry in resolving interface discrepancies is not without a price.
When a bus structure is implemented between a configuration of discrete and/or co-integrated modules, it should be appreciated that the bus structure itself determines, to a significant extent, the highest speed at which the configuration may operate. If the bus structure incorporates logic circuitry, data is subjected to specific delays during any clock cycle. These specific delays are imposed solely by the logic circuitry. If any delay imposed by logic circuitry is longer than the clock cycle, the configuration will fail to operate properly unless the clock speed is adjusted (i.e., reduced) whereby to disadvantageously inhibit the overall data throughput of a particular system.
In spite of this disadvantage, however, logic circuitry forming part of the bus structure remains as the standard approach in resolving the complexity of interface problems between co-integrated modules in an IC. At the same time, it should be noted that this approach has proven to be effective when used in producing relatively small IC""s, since bus related problems can be traced in a relatively straightforward manner by observing the overall operation of the chip. In a very large scale IC, however, the complex interactions between the modules in combination with other factors such as, for example, the immense numbers of signals which are present essentially eliminate the possibility of utilizing a simplistic troubleshooting technique. Moreover, other concerns come into play with regard to IC implementations at the very large scales contemplated herein, as will be seen immediately hereinafter.
It should be mentioned that delay times are introduced by factors other than interfacing logic circuitry. For instance, loading (i.e., the number of loads driven by a particular line) and the physical length of the bus structure each cause delays. With particular regard to the design of very large scale IC""s, which use the aforedescribed modular approach, bus loading and length are some of the most unpredictable and difficult to control variables. For example, the number of modules can vary from one implementation to the next and/or the physical distribution of the modules on the chip can vary. Thus, the addition of logic circuitry to the bus structure further complicates the design process by adding still more unpredictability to an already substantially unpredictable area.
As will be seen hereinafter, the present invention provides a highly advantageous bus arrangement and associated method which eliminate the need for logic circuitry within the bus arrangement so as to maximize the clock rate at which a particular configuration of integrated and/or discrete digital modules may operate in accordance with a reliable design approach.
As will be described in more detail hereinafter, there is disclosed herein a bus arrangement and an associated method. The bus arrangement is used in a digital system including three or more modules, which are configured for sending and/or receiving data using one or more respective inputs and/or outputs. The bus arrangement includes an input synchronization arrangement having a plurality of first, input latches. Each input latch includes an input terminal and an output terminal such that each module input is connected with the output terminal of an associated input latch. The bus arrangement also includes an output synchronization arrangement having a plurality of second, output latches each of which includes an input terminal and an output terminal such that each module output is connected with the input terminal of an associated output latch. An interconnection arrangement is provided for electrically interconnecting the output terminals of certain output latches with the input terminals of certain input latches in a predetermined way for transferring data between the modules such that the data does not encounter logic circuitry between the certain input and output latches.
In one aspect of the present invention, a single master clock signal is provided to the modules of the system. Using a first one of the modules, data is generated for use by a second one of the modules. During a first cycle of the master clock signal, data generated by the first module is latched and, thereafter, transferred to all other modules via the bus arrangement. During a second cycle of the master clock signal, the transferred data is latched at all modules other than the first module such that the transferred data is available for use by the intended, second module.